G, D.; H.B, M. R.; R, A. Resource efficient design of 16 x 16 multiplier by Block RAM generalized to n x n multiplier realized in FPGA. International Research Journal of Multidisciplinary Technovation, [S. l.], v. 7, n. 5, p. 75–93, 2025. DOI: 10.54392/irjmt2556. Disponível em: https://journals.asianresassoc.org/index.php/irjmt/article/view/2062. Acesso em: 19 may. 2026.