Design and Analsyis of 31-Level Asymmetric Cascaded H-Bridge Multilevel Inverter with Reduced Number of Switches

Received: 02-05-2020 Accepted: 23-09-2020 Abstract: A new multilevel inverter with less no of power switches is proposed. This is based on cascaded H-bridge topology. The design and analysis of 31level reduced switch inverter with different modes of operation are presented in this paper. The proposed inverter is asymmetric in nature and it uses unequal DC voltage sources. PD-PWM modulation technique has been used here to get proper switching. The proposed idea has been validated through simulation and the received results provides better efficiency, less low order harmonics and less switching losses.


Introduction
Multilevel inverter is a new domain of power converters used extensively in high and medium power applications such as integration of renewable energy resources, FACTS devices and so on [1][2][3]. The obtained output voltage waveform is nearly sinusoidal. In power electronic applications multilevel inverters are becoming popular as they have the good ability to meet the more demand of power rating and power quality associated with reduced harmonic distortion and lower electromagnetic interference. Multilevel inverter has the ability to operate with both fundamental and high switching frequency [1,[5][6][7][8][9]. Basically, there are three different topologies employed for Multilevel inverter: Neutral point clamp MLI (NPC), Flying capacitor MLI (FC) and Cascaded H-bridge MLI (CHB) [1,10]. In this the Cascaded H-bridge topology has gained a lot of interest because of its simplicity and modularity with the limitation of separate DC sources for each module when compared with other topologies such as NPC and FC [1]. On the basis of magnitude of DC voltages, CHB topology fall into two categories: Symmetric CHB and Assymetric CHB. The asymmetric topology utilizes a smaller number of switches, DC sources and diodes for same voltage levels as compared to symmetric topology [1]. The proposed MLI topology has more advantages than the existing topologies as the number of switching devices and total harmonic distortion are reduced.
In asymmetric multilevel inverter, DC source magnitudes are unequal and it is designed as to maintain a ratio of 1:2:4:8 [11][12][13][14][15][16]. A 2Khz multiple carrier signal is used to develop phase disposition pulse width modulation (PD-PWM). In this paper, level shifted PWM topologies with reduced no of switches which uses separate DC sources has been designed. The no of switches and no of levels are represented as follows N_Level = 2(n+1) -1 N_MOSFET = n+4 where n-no of DC sources.
The DC source magnitudes are designed with binary form of voltage such as 3V, 6V, 12V and 24V.

Proposed System
This section presents a detailed description of the proposed system which has additional features with added flexibility to that of the existing systems. It is implemented with a set of switch, diode and DC source at the input side of the circuit which produces higher output voltage level.

Switching Modes of Operation
Based on the gating signals, the four MOSFET switches in different times to create 31 different voltage levels which are shown in this section.  Switch S1, S2, S3, S4, S5 and S6 is ON, the voltage is maximum +Vdc across the load.  Switch S1, S3, S4, S5 and S6 is ON, the voltage is +13Vdc/15 across the load.

Mode 14:
Switch S2, S5 and S6 is ON, the voltage is +2Vdc/15 across the load. Switch S1, S5 and S6 is ON, the voltage is +Vdc/15 across the load.

Mode 16a:
The zero-output voltage level is produced by turning ON switch S5 and S7.

Mode 16b:
The zero-output voltage level is produced by turning ON switch S6 and S8.

Modulation Technique
The pulse width modulation (PWM) uses a fixed DC input voltage which is given to the inverter and produces a controlled AC output voltage by adjusting ON-OFF periods of inverter components which can be exercised as a control for the output voltage within the inverter itself.

Phase Disposition Pulse Width Modulation
This is a level shifted multiple carrier pulse width modulation technique with all carrier signals in same phase.

Fig 35. PD-PWM Technique
The reference signal is a sinusoidal wave of frequency 50Hz which is compared with triangular carrier waves of frequency 2Khz. The resultant output acts as gate signals for the MOSFETS.

Simulation and Results
The circuit diagram simulated in MATLAB is shown in Fig. 36.
The PWM control signals are generated in the subsystem block.
The switching pulses given for the switches S1, S2, S3 and S4 respectively is shown in Fig. 38. The switching pulses for H-Bridge is shown in Fig. 39.
The circuit is simulated in MATLAB for different loads like R load of 400Ω and RL load of 400Ω, 20mH. The results obtained for R anRL load are shown in Fig. 40 and Fig. 41 respectively.
The THD analysis for both the loads are observed and analysed to see the effects of change in loading which are shown in Fig. 42 and Fig. 43.

Conclusion
The proposed multilevel inverter with reduced number of switches can be implemented for medium and high-power industrial applications. The basic operation of the proposed MLI topology and the generation of required voltage level has been explained. The effective reduction of THD is achieved without using any filter in the circuit. The PD-PWM switching technique is simulated in